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Ieee Transactions On Very Large Scale Integration (vlsi) Systems

Ieee Transactions On Very Large Scale Integration (vlsi) SystemsSCIE

国际简称：IEEE T VLSI SYST  参考译名：超大规模集成 (vlsi) 系统上的 Ieee 事务

  • 中科院分区

    2区

  • CiteScore分区

    Q1

  • JCR分区

    Q2

基本信息：
ISSN：1063-8210
E-ISSN：1557-9999
是否OA：未开放
是否预警：否
TOP期刊：是
出版信息：
出版地区：UNITED STATES
出版商：Institute of Electrical and Electronics Engineers Inc.
出版语言：English
出版周期：Bimonthly
出版年份：1993
研究方向：工程技术-工程：电子与电气
评价信息：
影响因子：2.8
H-index：95
CiteScore指数：6.4
SJR指数：0.937
SNIP指数：1.516
发文数据：
Gold OA文章占比：7.13%
研究类文章占比：99.59%
年发文量：241
自引率：0.0714...
开源占比：0.0933
出版撤稿占比：0
出版国人文章占比：0.15
OA被引用占比：0
投稿咨询 加急见刊
英文简介 期刊介绍 CiteScore数据 中科院SCI分区 JCR分区 发文数据 常见问题

英文简介Ieee Transactions On Very Large Scale Integration (vlsi) Systems期刊介绍

The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

期刊简介Ieee Transactions On Very Large Scale Integration (vlsi) Systems期刊介绍

《Ieee Transactions On Very Large Scale Integration (vlsi) Systems》自1993出版以来，是一本工程技术优秀杂志。致力于发表原创科学研究结果，并为工程技术各个领域的原创研究提供一个展示平台，以促进工程技术领域的的进步。该刊鼓励先进的、清晰的阐述，从广泛的视角提供当前感兴趣的研究主题的新见解，或审查多年来某个重要领域的所有重要发展。该期刊特色在于及时报道工程技术领域的最新进展和新发现新突破等。该刊近一年未被列入预警期刊名单，目前已被权威数据库SCIE收录，得到了广泛的认可。

该期刊投稿重要关注点：

Cite Score数据（2024年最新版）Ieee Transactions On Very Large Scale Integration (vlsi) Systems Cite Score数据

  • CiteScore：6.4
  • SJR：0.937
  • SNIP：1.516
学科类别 分区 排名 百分位
大类：Engineering 小类：Electrical and Electronic Engineering Q1 195 / 797

75%
大类：Engineering 小类：Hardware and Architecture Q2 51 / 177

71%
大类：Engineering 小类：Software Q2 124 / 407

69%

CiteScore 是由Elsevier(爱思唯尔)推出的另一种评价期刊影响力的文献计量指标。反映出一家期刊近期发表论文的年篇均引用次数。CiteScore以Scopus数据库中收集的引文为基础，针对的是前四年发表的论文的引文。CiteScore的意义在于，它可以为学术界提供一种新的、更全面、更客观地评价期刊影响力的方法，而不仅仅是通过影响因子(IF)这一单一指标来评价。

历年Cite Score趋势图

中科院SCI分区Ieee Transactions On Very Large Scale Integration (vlsi) Systems 中科院分区

中科院 2023年12月升级版 综述期刊：否 Top期刊：否
大类学科 分区 小类学科 分区
工程技术 2区 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：电子与电气 2区 3区

中科院分区表 是以客观数据为基础，运用科学计量学方法对国际、国内学术期刊依据影响力进行等级划分的期刊评价标准。它为我国科研、教育机构的管理人员、科研工作者提供了一份评价国际学术期刊影响力的参考数据，得到了全国各地高校、科研机构的广泛认可。

中科院分区表 将所有期刊按照一定指标划分为1区、2区、3区、4区四个层次，类似于“优、良、及格”等。最开始，这个分区只是为了方便图书管理及图书情报领域的研究和期刊评估。之后中科院分区逐步发展成为了一种评价学术期刊质量的重要工具。

历年中科院分区趋势图

JCR分区Ieee Transactions On Very Large Scale Integration (vlsi) Systems JCR分区

2023-2024 年最新版
按JIF指标学科分区 收录子集 分区 排名 百分位
学科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 23 / 59

61.9%
学科：ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 151 / 352

57.2%
按JCI指标学科分区 收录子集 分区 排名 百分位
学科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 26 / 59

56.78%
学科：ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 149 / 354

58.05%

JCR分区的优势在于它可以帮助读者对学术文献质量进行评估。不同学科的文章引用量可能存在较大的差异，此时单独依靠影响因子(IF)评价期刊的质量可能是存在一定问题的。因此，JCR将期刊按照学科门类和影响因子分为不同的分区，这样读者可以根据自己的研究领域和需求选择合适的期刊。

历年影响因子趋势图

发文数据

2023-2024 年国家/地区发文量统计
  • 国家/地区数量
  • USA300
  • CHINA MAINLAND163
  • India72
  • Taiwan70
  • South Korea67
  • Canada46
  • GERMANY (FED REP GER)42
  • Singapore38
  • Iran36
  • Japan24

本刊中国学者近年发表论文

  • 1、A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder

    Author: Bai, Fujun; Wang, Song; Jia, Xuerong; Guo, Yixin; Yu, Bing; Wang, Hang; Lai, Cong; Ren, Qiwei; Sun, Hongbin

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 128-141. DOI: 10.1109/TVLSI.2022.3219437

  • 2、A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-mu W Embedded RRAM and Reconfigurable Strong PUF

    Author: Ren, Qirui; Huo, Qiang; Chen, Zhisheng; Gao, Qi; Wang, Yiming; Yang, Yiming; Wu, Hao; Fu, Xiangqu; Xu, Xiaoxin; Luo, Qing; Gao, Jianfeng; Chen, Chengying; Zhao, Xiaojin; Lei, Dengyun; Wang, Xinghua; Zhang, Feng; Chen, Yong; Mak, Pui-In

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 243-252. DOI: 10.1109/TVLSI.2022.3222522

  • 3、A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique

    Author: Wang, Yujia; Zhang, Jincheng; Chen, Yong; Ren, Junyan; Ma, Shunli

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 233-242. DOI: 10.1109/TVLSI.2022.3225967

  • 4、Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method

    Author: Wang, Jun; Luo, Yuhuan; Guo, Wenting; Wu, Feng; Chu, Xiuqin

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 210-218. DOI: 10.1109/TVLSI.2022.3225533

  • 5、Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors

    Author: Tan, Hongbing; Tong, Gan; Huang, Libo; Xiao, Liquan; Xiao, Nong

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 253-266. DOI: 10.1109/TVLSI.2022.3226185

  • 6、A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs

    Author: Qiu, Lei; Meng, Tianyi; Yao, Bingbing; Du, Zihao; Yuan, Xiaohua

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 152-156. DOI: 10.1109/TVLSI.2022.3224237

  • 7、BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks

    Author: Li, Hongyan; Lu, Hang; Wang, Haoxuan; Deng, Shengji; Li, Xiaowei

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 90-103. DOI: 10.1109/TVLSI.2022.3221732

  • 8、Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

    Author: Gao, Zhen; Shi, Jinchang; Liu, Qiang; Ullah, Anees; Reviriego, Pedro

    Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 142-146. DOI: 10.1109/TVLSI.2022.3224137

投稿常见问题

通讯方式：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, USA, NJ, 08855-4141。

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